Fast ring-out digital storage circuit

ABSTRACT

A static storage element distorts metastable feedback signals in an unbalanced feedback loop with the resulting metastable signals eroding and being suppressed as they circulate in the loop. The element exhibits a predetermined output state subsequent to suppression of the eroded signals.

FIELD OF THE INVENTION

The invention pertains to multi-state circuits. More particularly, theinvention pertains to such circuits which minimize the duration ofmetastable states.

BACKGROUND OF THE INVENTION

Known multi-state storage circuits often incorporate one or more activeelements combined with feedback circuitry to produce a plurality ofoutput states. Reliable achievement of an expected output state inresponse to a set of inputs can be critical to downstream circuitperformance.

FIG. 1 illustrates a known realization of an exemplary multi-statestorage circuit 10, a D-type flip-flop. The realization of FIG. 1 is amaster, M, slave, S, configuration implemented using inverters with aclock input, line 16 and a data input, line 18.

In FIG. 1, inverter 30 provides an inverted clock signal. Circuitelements 34–40 constitute the “master”, M, latch. Circuit elements 44–50make up the “slave”, S, portion. Together, the master and slave create apositive edge triggered behavior, with respect to clock signals CLK online 16.

Elements 34 and 40 are known non-inverting transmission or pass gateswhich resemble switches that are either open circuited or conducting.They are connected in an opposite manner to the CLK or inverted CLKsignal such that one element is open and the other is conducting at anygiven time. This prevents contention at the input of inverter 36.

Elements 36 and 38 are inverters which provide a stable feedback loop 42when CLK is “high” (logic 1 state). In this case, element 34 is open and40 is conducting.

When CLK is “low” (logic 0 state), the master stage M is sampling the Dinput. Element 34 is conducting. Element 40 is open circuited. The slavesection S, behaves identically but CLK is driven by an inverted clocksignal from inverter 30.

During a critical time when the CLK signal, on line 16, rises, themaster M transitions from a transparent to latching state while theslave S goes from the latching to transparent state. For reliableoperation, the CLK signal must not rise before the logic state of the Dinput, line 18, has had enough time to pass through elements 34, 36, and38. This ensures an orderly transition to the latching state since theoutput of element 40 will drive the input of inverter 36 with the samelogic state that element 34 had been conducting.

A metastable condition can occur when the CLK signal rises before thelatest D input state change on line 18 has had time to traverse thefeedback loop to the output of inverter 38. In this case, multiple logicstates can co-exist in the feedback loop 42 when the master section Menters the latching state. In this instance, the feedback loop 42 formsan oscillator that can ring for an unpredictable amount of time, ametastable state, and resolve to an unpredictable final state.

The length of time that the oscillation will persist is related to theduty cycle distortion experienced by the signal as it completes onecircuit through the feedback loop 42. The lower the duty cycledistortion, the longer the oscillation will remain.

For optimal flip-flop performance, designers have used symmetricallybalanced inverters and pass gates. In such designs, key flip-flopparameters such as set-up and hold times are equal for both logic 1 and0 data conditions. Balanced inverters and pass gates also result in lowduty cycle distortion in the feedback path. Hence, known flip-flopdesigns can have very low duty cycle distortion and inadvertentlyprovide feedback paths that can remain in the metastable state forrelatively long periods of time relative to the period of the CLKsignal. The existence of metastable states in digital circuits isinconsistent with reliable operation of such circuits.

There is thus a continuing need for multi-state circuits which promptlysuppress metastable states for a given maximum sampling rate. Preferablysuch circuits could be fabricated using known techniques so as to avoidhaving to develop new manufacturing methodologies. Additionally, itwould be preferred if such circuits could be implemented with minimaladditional components.

SUMMARY OF THE INVENTION

In one embodiment of the invention a circuit has an input and a storageelement coupled at least to the input. The storage element has anunbalanced feedback loop that produces a predetermined degree of dutycycle distortion of electrical signals circulating in the feedback loop.

Numerous other advantages and features of the present invention willbecome readily apparent from the following detailed description of theinvention and the embodiments thereof, from the claims and from theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior art D-type flip-flop;

FIG. 2 is a block diagram of a storage circuit in accordance with thepresent invention;

FIG. 3A illustrates a circuit with unbalanced inverters;

FIG. 3B is a plurality of waveforms illustrating performance of thecircuit of FIG. 3A;

FIG. 4 is a schematic diagram illustrating details of an embodiment ofthe storage circuitry of the FIG. 2;

FIGS. 5A and 5B are wave forms illustrating various operationalcharacteristics of the storage circuitry of FIG. 4;

FIG. 6 is a schematic diagram illustrating another embodiment of aD-type storage circuit; and

FIG. 7 is a schematic diagram of an R-S-type storage circuit inaccordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

While embodiments of this invention can take many different forms,specific embodiments thereof are shown in the drawings and will bedescribed herein in detail with the understanding that the presentdisclosure is to be considered as an exemplification of the principlesof the invention and is not intended to limit the invention to thespecific embodiments illustrated.

FIG. 2 illustrates a static, multi-state circuit 200 which embodies thepresent invention. The circuit 200 includes a data input line 202 whichcould carry asynchronous digital signals and a clock input line 204. Theclock signals on the line 204 could be used to drive other circuitry.

The circuit of FIG. 2 purposely degrades trapped feedback pulses whichin turn will terminate any metastable state exhibited within aquantifiable maximum ring-out time. This in turn facilitates defining aminimum sampling clock wherein the storage circuitry could be operatedwith substantially error-free performance.

In one embodiment of the invention, distortion in the feedback path canbe produced by changing parameter ratios of transistors in the feedbackpath to provide unbalanced circuit performance. Where two inverters areused in the feedback path, they can be ratioed in the opposite way, forexample by changing switching thresholds, (increasing in one inverter,decreasing in the other) such that the trapped feedback pulse isrepeatedly narrowed, and ultimately suppressed, as it passes througheach inverter.

The circuit 200 incorporates a static, multi-state storage circuitgenerally indicated at 210 which incorporates a feedback loop 212. Itwill be understood by those of skill in the art that the storage circuit210 could be implemented with a variety of circuit configurations suchas flip-flops or latches implemented as MOS-type storage elements,CMOS-type storage circuits, ECL-type storage circuits, TTL-type storagecircuits or capacitively coupled storage circuits and the like withoutdeparting from the spirit and scope of the present invention. Neitherthe specific circuit designs nor manufacturing technologies arelimitations of the invention.

The feedback loop 212 incorporates at least first and second circuitelements 218 a and 218 b. The circuit elements 218 a, b couldincorporate inverters, as well as non-inverting switches, of a typeknown to those of skill in the art. Output line 220 reflects the stateof circuit 200.

The elements 218 a, b are unbalanced, as described in more detailsubsequently. This unbalancing distorts signals in the feedback path 212to absorb metastable events, which may occur, within just a fewoscillations or periods. Since the frequency of oscillation in ametastable state is equal to the transit time of pulses through thefeedback loop 212, maximum oscillation ring-out time can be determinedand reduced by adjusting the distortion of the duty cycle. Suppressionof the metastable events in accordance with the present inventionproduces improved performance without introducing additional circuitelements.

The unbalanced, asymmetrical, storage circuits of the present inventioncan also be incorporated as the slave section, S, of master-slavestorage devices to minimize the duration for metastable states. Unlikeprior art solutions, storage circuits which embody the present inventionsuppress metastable events within a predictable number of cycles makingit possible to design highly reliable synchronizing circuits with errorprobabilities approaching zero.

Achieving an unbalanced feedback loop in a storage circuit or devicesuch as storage device 210 can be accomplished by adjusting relativeparameter values of those transistors or resistors in the respectivefeedback loop 212 which are responsible for propagating either rising orfalling edges of electrical pulses circulating in the feedback loop 212.As explained subsequently, the loop can be unbalanced to drive theoutput value to a predetermined high or low state within a known timeinterval.

FIGS. 3A and 3B together illustrate the effects of unbalancing exemplaryinverters. It will be understood that the inverters could be implementedin a variety of technologies, and with varying circuit details, withoutdeparting from the spirit and scope of the present invention.

FIG. 3A illustrates a string of series connected inverters I-1, I-2, I-3and I-4. Each of the inverters has been unbalanced such that itsswitching threshold has been shifted either up or down from a normalbalanced state. The balanced threshold T would be midway between theelectrical signals corresponding to a logical one and a logical zero,for example, five volts and zero volts. Alternate inverters I-1, I-3have been unbalanced so as to shift their respective thresholds T-1, T-3in the opposite direction from that of the intervening inverters I-2,I-4, T-2, T-4.

FIG. 3B is an exemplary timing diagram illustrating the consequences ofunbalancing inverters I-1. . . I-4 as in FIG. 3A. As illustrated in FIG.3B, a pulse train 100 is coupled as an input to inverter I-1.

A second waveform 102 is the output from inverter I-1 in response to theinput thereto, waveform 100. As illustrated in FIG. 3B, waveform 102 hasbecome distorted and asymmetrical with the higher level increasing induration due to the unbalanced increased switching threshold T-1 ofinverter I-1. Waveform 104 illustrates the output of inverter I-2, whichhas a reduced threshold T-2, the input to inverter I-3. Waveform 104exhibits distorted, expanded low voltage compared to the input 100 toinverter I-1.

Waveform 106, the output of inverter I-3, has been distorted to theextent that the amplitude variations of waveform 100, input to inverterI-1, have been completely suppressed or eroded. Thus, unbalancingcircuits, such as inverters, as illustrated in FIGS. 3A, B, can producedistorted waveforms and result in suppression of pulses in thedownstream portions of the circuitry. In general in a digital system thedistortion exhibited by waveform 106 is undesirable and is to be avoidedas the information carried by signal 100 has been lost.

FIG. 4 illustrates details of an exemplary two state, staticimplementation of storage element 210. For best mode purposes, circuit210 has been illustrated as implemented with CMOS circuit elements. Itwill be understood that other types of CMOS or MOS circuit elements,bipolar circuit elements and/or alternate latch or flip-flop circuitdesigns all, without limitation, come within the spirit and scope of theinvention.

Element 218 a, a complementary CMOS inverter of a known type,incorporates MOS transistors 236 a, b. Element 218 b, a complementaryCMOS inverter of a known type, incorporates MOS transistors 328 a, b.Loop 212 includes CMOS transmission gate 218 c.

The inverters 218 a, b and switch 218 c could be realized using standardCMOS transistor fabrication techniques. Inverter 218 a incorporates aP-type CMOS transistor 236 a and an N-type CMOS transistor 236 b.Transistors 236 a, b are coupled in series with a common output on line220 as is conventional.

Outputs from inverter 218 a, line 220 are coupled as inputs to inverter218 b. Inverter 218 b incorporates a P-type CMOS transistor 238 a whichis series coupled to an N-type CMOS transistor 238 b also as isconventional. A common output from inverter 218 b is in turn coupled tonon-inverting transmission gate 218 c which incorporates a P-type CMOStransistor 240 a and an N-type CMOS transistor 240 b. Output from thegate 218 c is coupled back as an input to inverter 218 a via line 202.

The transistor pairs 236 a, b, 238 a, b and 240 a, b are unbalanced byadjusting respective parameter values, such as their respective gains,to increase or decrease their respective switching thresholds goingaround the loop 212 so as to erode or suppress metastable pulses asillustrated in FIG. 5B. For example and without limitation, the gategeometries of the respective pairs, the thickness of the respective gateoxide layers of the respective pairs, the dopant density of therespective pairs can be adjusted to force the respective switchingthreshold from a balanced value to an unbalanced value as illustrated inFIG. 3A. Other parameters could also be unbalanced and such unbalancingfalls within the spirit and scope of the invention.

By providing P-type transistors 236 a, 238 a and 248 a with greater gainvalues than N-type transistors 236 b, 238 b and 240 b distortion as inFIG. 5A can be produced. This distortion erodes or degrades metastateoscillations as they circulate in loop 212 causing them to ceaserelatively quickly and resulting in a stable high or logical one outputstate on the line 36 b′. Alternately, unbalancing the respective pairs236 a, b; 238 a, b; and 240 a, b; in the opposite manner will produce afeedback loop 212 which erodes or terminates metastable oscillations toa logical zero or low output state on the line 220 as in FIG. 5B.Elements 218 b and 218 c could be replaced with a single tristateinverter to reduce component count without departing from the spirit andscope of the invention.

The circuitry of FIG. 4 could be used to implement the master section Mof a master/slave flip-flop if desired. This implementation wouldaddress the source of any metastable behavior. Additionally, thecircuitry of FIG. 4 could also be used to implement the slave portion Sof a D-type or master/slave flip-flop as in FIG. 1. In the slavefeedback loop, the time between active and inactive clock edges wouldnormally be expected to be longer than the maximum ring-out time of thefeedback loop 212.

It will be understood that a variety of multi-state circuits such asT-type or R-S flip-flops could be implemented using unbalancedconfigurations without departing from the spirit and scope of theinvention. Other multi-state circuits which include feedback could alsobe implemented with unbalanced feedback loops.

FIG. 6 illustrates a D-type MOS latch 300 which has an alternatearchitecture and which embodies the present invention. The latch 300 hasa D-input 302 and a clock input 304. An inverter 306 provides aninverted clock signal. An output, Q, that tracks the D-input is providedon line 308.

The latch 300 incorporates a first inverter 310 which receives inputsfrom both the D-input 302 and the clock signal 304. Output from theinverter 310 is coupled via line 316 as an input to inverter 312 and anoutput of inverter 314. An output 312 a of inverter 312 is coupled to aninput to inverter 314.

The inverter 310 incorporates transistors 321, 322, each of which is aP-channel MOSFET. It also incorporates N-channel MOSFETs 323, 324.

The inverter 312 incorporates a P-channel MOSFET 341 and an N-channelMOSFET 342. The inverter 314 incorporates P-channel MOSFETs 331 and 332and N-channel MOSFETs 333 and 334. As illustrated, input line 312 a iscoupled to transistors 331 and 334 in inverter 314.

When the clock signal on line 304 goes high, transistors 322 and 323turn on. The signal on the D-input line 302 is inverted and coupled by aline 316 to inverter 312. During this time interval, inverter 314 isturned off. The inverter 312 inverts the signal on the line 316 andcouples it to output line 308 as the Q output for the device.

When clock on line 304 goes low, gate 310 turns off and does not outputa signal. At that time, gate 314 is enables and couples an invertedrepresentation of the signal on line 312 a to line 316. This provides astable output of the value of the D-input on the line 308.

In accordance with the invention, to suppress metastable states, thefeedback path 212-1 involving inverters 312 and 314 can be unbalanced byincreasing the switching threshold of inverter 312 and decreasing thatof inverter 314 as discussed above, or alternately, decreasing theswitching threshold of inverter 312 and increasing the switchingthreshold of inverter 314. Using the process as described above,metastable states can be suppressed or eroded.

FIG. 7 illustrates an R-S-type storage circuit 400 having yet anothercircuit topology and which embodies the present invention. The circuit400 includes two cross connected, two input, NAND gates 402 and 404which are substantially identical structurally, but, in accordance withthe invention, are adjusted so as to exhibit an unbalanced feedback loopfor the purpose of suppressing metastable states.

The NAND gate 402 includes first and second inputs 406 a, b and anoutput 406 c, the Q output. The NAND gate 404 also has inputs 408 a, band an output 408 c which is coupled back to input 406 b of gate 402.Similarly, the output of gate 402, line 406 c is coupled back to input408 a of gate 404. The cross-connected gates 402, 404 exhibit theexpected behavior of an R-S-type storage circuit.

NAND gate 402 incorporates first and second P-channel transistors 412 a,b and first and second N-channel transistors 414 a, b. As illustrated inFIG. 7, the four transistors 412 a, b and 414 a, b are interconnected soas to implement the NAND function as would be understood by those ofskill in the art. Additionally, transistors 412 b and 414 b are in afeedback loop being coupled via line 406 b to output line 408 c of gate404. Gate 404 has a similar pair of transistors coupled in a feedbackloop via line 408 a and output 406 c.

Circuit 400, in addition to exhibiting first and second states inresponse to input set and reset signals can also exhibit undesirablemetastable states where those signals change substantially andsimultaneously, for example from a low level to a high level.

In accordance with the present invention, the feedback loops in circuit400 can be unbalanced, as discussed above. For example, a switchingthreshold of one pair of transistors, such as transistors 412 b, 414 b,gate 402 can be increased or decreased while a switching threshold ofthe corresponding pair of transistors in gate 404 can be decreased orincreased thereby producing the desired unbalanced feedback loop. Thiswill in turn erode and suppress any metastable pulses as discussedpreviously.

As illustrated by the above exemplary embodiments, a variety of circuittopologies come within the spirit and scope of the present invention.Similarly, alternate ways to provide an unbalanced feedback loop, hence,the desired duty cycle distortion, also come within the spirit and scopeof the invention.

As is known, MOS processes produce a range of P-type and N-typetransistor performance. The extent of the intentional mismatch should besuch that the desired degree of duty cycle distortion is maintained forall fabrication outcomes.

In the worst case output, the duty cycle distortion will be weakest andthe ring-out time will be the longest. As would be understood by thoseof skill in the art, the mismatch factor required to achieve a maximumdesired ring-out time is determinable for this circumstance. It sets alower limit on the period of the clock signal for the desired reliableoperation.

From the foregoing, it will be observed that numerous variations andmodifications may be effected without departing from the spirit andscope of the invention. It is to be understood that no limitation withrespect to the specific apparatus illustrated herein is intended orshould be inferred. It is, of course, intended to cover by the appendedclaims all such modifications as fall within the scope of the claims.

1. A circuit comprising: a data input; and a storage element coupled atleast to the data input, the storage element having first and secondunbalanced feedback loops, each of which produces a predetermined degreeof duty cycle distortion of electrical signals circulating in therespective feedback loop at least one of the feedback loops including atleast a non-inverting gate having an unbalanced switching characteristicto contribute to the duty cycle distortion.
 2. A circuit as in claim 1which includes at least one switching element which comprises acomplimentary pair of transistors where the transistors exhibitdifferent respective parameter values which promote absorption ofmetastable events in the feedback loop.
 3. A circuit as in claim 1 wherethe storage element includes first and second unbalanced inverterscoupled together via a respective feedback loop with the gate coupledbetween the inverters in the respective feedback loop.
 4. A circuit asin claim 3 where at least one of the inverters comprises first andsecond asymmetrical switching elements.
 5. A circuit as in claim 4 wherethe switching elements comprise complementary transistors.
 6. A circuitas in claim 1, where the storage element comprises a flip-flop having atleast a first set of semiconductor elements and a second set ofsemiconductor elements that are counterparts to the first set ofsemiconductor elements, the first set of semiconductor elements beingmismatched to the second set of semiconductor elements with theunbalanced gate therebetween.
 7. A circuit as in claim 6 where thesemiconductor elements include P-type transistors and N-typetransistors, and wherein P-type transistors and N-type transistorsbiased in opposite directions are mismatched to produce an unbalancedswitching characteristic.
 8. A circuit as in claim 1 where the storageelement includes first and second latches coupled in series, and whereineach of the latches has a feedback loop and a respective unbalancedparameter wherein a feedback signal circulating in a respective feedbackloop has a predetermined degree of distortion and where the gate islocated in a selected one of the feedback loops.
 9. A circuit as inclaim 8 where the latches each include at least first and secondinverting elements, each of the inverting elements having a distortionproducing set of parameters with one set of parameters producing a firstdistortion and with the other set of parameters producing an oppositedistortion of the feedback signal.
 10. An apparatus as in claim 9 whereduty cycle distortion in the feedback loop absorbs metastable eventswithin a predetermined number of oscillations of signals in the feedbackpath.
 11. A metastable state suppressing circuit comprising: a firstswitching element, and a second switching element, the two switchingelements coupled to form at least a bi-state configuration with eachswitching element having a switching parameter value displaced from acommon balanced parameter value with one switching element's parametervalue greater than the balanced value and the other switching element'sparameter value less than the balanced value with the switchingparameters comprising switching thresholds with the one switchingelement's switching threshold exceeding a common balanced thresholdvalue and the other switching element's switching threshold less thanthe common balanced threshold value.
 12. A circuit as in claim 11 wherethe switching elements are selected from a class which includes CMOScircuits, emitter coupled logic-type circuits, MOS-type circuits,gallium arsenide-type circuits and bi-polar transistor type circuits.13. A circuit as in claim 11 where the unbalanced switching parametervalues terminate a metastable state exhibited by the bi-stateconfiguration.
 14. A circuit as in claim 13 where the bi-stateconfiguration exhibits a predetermined output state and another stateand with the respective switching parameter values displaced from thebalanced parameter value to cause the bi-state configuration to exhibitthe predetermined output state when the metastable state terminates. 15.A device comprising: first and second inverter circuits, each invertercircuit having an input and an output, each input of each invertercircuit is coupled to the output of the other inverter circuit to form afirst bistable unit, each inverter circuit defines a switchingthreshold, the switching threshold for one inverter is offset from theswitching threshold for the other inverter, the switching thresholdseach introduce respectively first and second types of duty cycledistortion such that the offset between the thresholds suppressesoscillating signals circulating through the inverters and, an isolationgate is coupled between the inverters and where each inverter receiveselectrical signals that vary over a predetermined range with the offsetbetween the thresholds less than the range of predetermined signals andwhere one threshold exceeds a midpoint of the range and the otherthreshold is less than the midpoint of the range.
 16. A device as inclaim 15 which includes third and fourth inverter circuits, each of thethird and fourth inverter circuitries has an input and an output witheach input of the third and fourth inverter coupled to an output of thefourth and third inverters to form a second bistable unit where thefirst and second bistable units implement a master-slave flip-flop. 17.A device as in claim 15 with the isolation gate having an unbalancedswitching characteristic to produce duty cycle distortion thatcontributes to suppressing oscillating signals circulating through theinverters.
 18. A device as in claim 17 where the duty cycle distortionof the gate corresponds to the type of duty cycle distortion of theinverter feeding signals to the gate.
 19. A device as in claim 15 wherethe thresholds vary from the midpoint of the range by a common amount.